The T20 FPGA features the high-density, low-power Efinix® Quantum® fabric wrapped with an I/O interface in a small footprint package for easy integration. T20 FPGAs support mobile, consumer, and IoT edge markets that need low power, low cost, and a small form factor. These FPGAs have hardened MIPI CSI-2 controllers with independent TX/RX. Additionally, they have hardened DDR DRAM controller that supports DDR3, LPDDR3, and LPDDR2. T20 FPGAs:
- Some packages have hardened MIPI CSI-2 interfaces for video and camera applications
- Some packages feature a hardened DDR DRAM interface for accessing off-chip memory devices
- Have LVDS pins that operate at 800 Mbps per lane
- Are built on a low-power 40 nm process
- Feature high-performance I/O supporting 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces
- Provide flexible on-chip clocking
- Have device configuration options including a standard SPI and JTAG interfaces
- Fully supported by the Efinity® software, an RTL-to-bitstream compiler
- Optional mask option, that allows you to eliminate the configuration device, thereby saving space and costs
- LQFP100F3 package features internal SPI flash memory for configuration bitstreams, non-volatile user data and RISC-V application code
Techn. Specifications
| Logic Elements: | 19728 |
| RAM: | 1044.48 kbites |
| RAM blocks (5Kb): | 204 |
| Multipliers: | 36 |
| Temperature range: | - 40° - 100° C |
VPE/Packaging Unit: 5 pcs.
Standard lead time: 8-12 weeks
